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TMS320C5515
www.ti.com
SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
Table 2-7. RESET, Interrupts, and JTAG Terminal Functions (continued)
SIGNAL
NAME
NO.
TYPE (1)
(2)
OTHER (3)
(4)
DESCRIPTION
IEEE standard 1149.1 test data output. The contents of the selected
register (instruction or data) are shifted out of TDO on the falling edge
of TCK. TDO is in the high-impedance (Hi-Z) state except when the
scanning of data is in progress.
For board design guidelines related to the emulation header, see the
–
XDS560 Emulator Technical Reference (literature number: SPRU589 ).
TDO
M7
O/Z
DV DDIO
BH
If the emulation header is located greater than 6 inches from the
device, TDO must be buffered.
Note: This pin may consume static power if configured as Hi-Z and not
pulled high or low. Prevent current drain by externally terminating the
pin. TDO pin will be Hi-Z whenever not doing emulation/boundary scan,
so an external pullup is highly recommended.
IEEE standard 1149.1 test data input. TDI is clocked into the selected
register (instruction or data) on a rising edge of TCK.
If the emulation header is located greater than 6 inches from the
IPU
device, TDI must be buffered. In this case, the input buffer for TDI
TDI
L7
I
DV DDIO
needs a pullup resistor connected to DV DDIO to hold this signal at a
BH
known value when the emulator is not connected. A resistor value of
4.7 k ? or greater is suggested.
The IPU resistor on this pin can be enabled or disabled via the
PDINHIBR2 register.
IEEE standard 1149.1 test clock. TCK is normally a free-running clock
signal with a 50% duty cycle. The changes on input signals TMS and
TDI are clocked into the TAP controller, instruction register, or selected
test data register on the rising edge of TCK. Changes at the TAP output
signal (TDO) occur on the falling edge of TCK.
TCK
M6
I
IPU
DV DDIO
BH
If the emulation header is located greater than 6 inches from the
device, TCK must be buffered.
For board design guidelines related to the emulation header, see the
XDS560 Emulator Technical Reference (literature number: SPRU589 ).
The IPU resistor on this pin can be enabled or disabled via the
PDINHIBR2 register.
IEEE standard 1149.1 reset signal for test and emulation logic. TRST,
when high, allows the IEEE standard 1149.1 scan and emulation logic
to take control of the operations of the device. If TRST is not connected
or is driven low, the device operates in its functional mode, and the
TRST
M9
I
IPD
DV DDIO
IEEE standard 1149.1 signals are ignored. The device will not operate
properly if this reset pin is never asserted low.
BH
IPU
For board design guidelines related to the emulation header, see the
XDS560 Emulator Technical Reference (literature number: SPRU589 ).
It is recommended that an external pulldown resistor be used in
addition to the IPD -- especially if there is a long trace to an emulation
header.
Emulator 1 pin. EMU1 is used as an interrupt to or from the emulator
system and is defined as input/output by way of the emulation logic.
An external pullup to DV DDIO is required to provide a signal rise time of
less than 10 μ sec. A 4.7-k ? resistor is suggested for most applications.
EMU1
M5
I/O/Z
DV DDIO
BH
For board design guidelines related to the emulation header, see the
XDS560 Emulator Technical Reference (literature number: SPRU589 ).
The IPU resistor on this pin can be enabled or disabled via the
PDINHIBR2 register.
Copyright ? 2010–2013, Texas Instruments Incorporated
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